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YSS932
AC3D3B
96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP
OUTLINE
YSS932 is one chip LSI consisting of three built-in blocks : SPDIF receiver (DIR), Dolby Digital (AC-3) / Pro Logic II & DTS decoder (Main DSP) and programmable sound fields processing DSP (Sub DSP). The Sub DSP is capable of realizing various sound fields, such as virtual surround by down-loading the program and coefficient from outside.
FEATURES
[ DIR Block ] * Sampling frequency: Two ranges are available including; 32k to 48kHz (normal rate) and 64k to 96kHz (double rate). * Provides master clock, 256fs, to DAC, ADC and the other peripheral devices. The clock output can be controlled with various modes determined by register settings. * Has a pin that indicates the double rate operation. * Every channel status and user data can be read through the microprocessor interface. * Has an output pin for interrupt that is activated by changing of the status information. * Internal operation frequency: 25MHz [ Main DSP Block ] * Dolby Digital (AC-3) / Pro Logic II and DTS decode. * High quality internal 24 bit DSP. * No external memory is required. (Memory for the center and surround channel signal delay is included.) * AC-3 Karaoke mode. * Supports compression mode at AC-3 / DTS decoding. * Included de-emphasis filter for the PCM signal. * Pro Logic II decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM signal. * Reads Dolby Digital / DTS decode information through the microprocessor interface. * Internal operation frequency: 30MHz
YAMAHA CORPORATION
YSS932 CATALOG CATALOG No.: LSI-4SS932A2 2003.2
YSS932
[ Sub DSP Block ] * Capable of realizing various sound fields, such as simulation surround, output configuration and virtual surround by downloading the programs from the microprocessor. * Adoption of the 32 bit floating-point DSP assuring highly accurate processing. * Up to 2.73 seconds delay at fs=48kHz achievable by adding DRAM or SRAM externally. * Internal operation frequency: 30MHz
[ Other Features ] * Connectable to almost all ADC and DAC by making appropriate settings to the control register. * Total of 16 general purpose input/output ports are provided. * 2 built-in PLL circuits for generation of operation clocks for DIR block and DSP blocks. * Power supply voltage: 2 power sources (2.5V for core logic section and 3.3V for I/O section) * Si-gate CMOS process * 128SQFP (YSS932-S)
Note:
"AC-3" and "Pro Logic II" are registered trademarks of Dolby Laboratories Licensing corporation. "DTS" is a registered trademark of DTS, Inc. Use of this LSI must be licensed by both Dolby Laboratories Licensing Corporation and DTS, Inc.
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YSS932
BLOCK DIAGRAM
SYNC/U
7
6
5
IPORT5-7
VMOD
DBL V
BSMOD
ERR BS
DDINSEL
UMOD
SYNC U
CMOD
FS128 C
DIRPCO DIRPRO
PLL
Clock for DIR Block (25MHz)
DIR
FS128/C
ERR/BS
DIRINT
DDIN3
DDIN2
DDIN1
DDIN0
/LOCK
DBL/V
DIRMCK DIRO Interface DIRBCK DIRWCK SDBCKI0 SDWCKI0 SDIASEL SDIACKSEL
DIRSDO SDIA
MainDSP XI XO CPO
(AC-3/ProLogicII/DTS decoder)
Microprocessor I/F
Control Register
PLL
Control Signal
SURENC KARAOKE MUTE CRC AC3DATA DTSDATA NONPCM ZEROFLG
SDIA Interface CRC
/SDBCKO
IPORT0-4
/CS SO SI SCK
Clock for DSP Block (30MHz)
SDOA Interface
L,R LS,RS C,LFE
SDOA0 SDOA1 SDOA2 SDIB0 SDIB1 SDIB2 SDIB3
OPORT0-7
SDIBSEL SDIBCKSEL
SDIB Interface RAMD0-15 CASN RASN RAMWEN RAMOEN RAMA0-17
External Memory Interface
SubDSP
OVFSEL OVFB END
Coefficient / Program RAM
OVFB/END
SDOB Interface
SDOBCKSEL
SDWCKI1
SDBCKI1
SDOB3
SDOB2
SDOB1
SDOB0
MPLOAD
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YSS932
PIN CONFIGRATION
TESTXI TESTXO VDD2 XO XI TESTMS TESTXEN IPORT0 IPORT1 IPORT2 IPORT3 IPORT4 DDIN0 DDIN1 DDIN2 DDIN3 VSS CPO AVDD DIRPCO DIRPRO AVSS TESTBRK TESTR1 TESTR2 VDD1 SDWCKI0 SDBCKI0 /SDBCKO SDIA SDOA2 SDOA1 SDOA0 SDIB3 SDIB2 SDIB1 SDIB0 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VSS /IC SCK SI SO /CS DIRINT /LOCK CRC SURENC VDD1 KARAOKE MUTE AC3DATA DTSDATA NONPCM VSS ZEROFLG OVFB/END RAMA17 RAMA16 RAMA15 RAMA14 RAMA13 RAMA12 VDD2
VSS RAMA11 RAMA10 RAMA9 RAMA3 RAMA4 RAMA2 RAMA5 RAMA1 RAMA6 RAMA0 RAMA7 RAMA8 VDD1 VSS RASN RAMOEN RAMWEN CASN RAMD15 RAMD14 RAMD13 RAMD12 RAMD11 RAMD10 RAMD9 RAMD8 VDD1 VSS RAMD7 RAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 VDD2
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VDD2 DIRSDO DIRWCK DIRBCK DIRMCK ERR/BS SYNC/U FS128/C DBL/V SDWCKI1 SDBCKI1 VSS SDOB3 SDOB2 SDOB1 SDOB0 VDD1 OPORT0 OPORT1 OPORT2 OPORT3 OPORT4 OPORT5 OPORT6 OPORT7 VSS
< 128SQFP TOP VIEW >
YSS932
PIN FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Name TESTXI TESTXO VDD2 XO XI TESTMS TESTXEN IPORT0 IPORT1 IPORT2 IPORT3 IPORT4 DDIN0 DDIN1 DDIN2 DDIN3 VSS CPO AVDD DIRPCO DIRPRO AVSS TESTBRK TESTR1 TESTR2 VDD1 SDWCKI0 SDBCKI0 /SDBCKO SDIA SDOA2 SDOA1 SDOA0 SDIB3 SDIB2 SDIB1 SDIB0 VSS VDD2 DIRSDO DIRWCK DIRBCK DIRMCK ERR/BS SYNC/U FS128/C DBL/V SDWCKI1 SDBCKI1 VSS SDOB3 SDOB2 SDOB1 SDOB0 VDD1 I/O I O O I I+ I+ I+ I+ I+ I+ I+ Is Is Is Is A A A I+ I+ I+ I+ I+ O I O O O I+ I+ I+ I+ O O O O O O O O I+ I+ O O O O Function LSI Test pin (must be connected to VSS) LSI Test pin (to be open) +2.5V power supply (for internal core logic) Crystal oscillator connection Crystal oscillator connection (24.576MHz) LSI Test pin (to be open) LSI Test pin (to be open) General purpose input port General purpose input port General purpose input port General purpose input port General purpose input port DIR: Digital audio interface data input 0 DIR: Digital audio interface data input 1 / General purpose input port DIR: Digital audio interface data input 2 / General purpose input port DIR: Digital audio interface data input 3 / General purpose input port Ground PLL filter connection +3.3V power supply (for DIR block) DIR: PLL filter connection DIR: PLL filter connection Ground (for DIR block) LSI Test pin (to be open) Initial Clear input for PLL in DSP block LSI Test pin (to be open) +3.3V power supply (for I/O) Word clock input for SDIA, SDOA, SDIB, SDOB Bit clock input for SDIA, SDOA, SDIB, SDOB Reverse clock output of DIRBCK or SDBCKI0 Input of bitstream or PCM data to Main DSP PCM data output from Main DSP (C, LFE) PCM data output from Main DSP (LS, RS) PCM data output from Main DSP (L, R) PCM data input 3 to Sub DSP PCM data input 2 to Sub DSP PCM data input 1 to Sub DSP PCM data input 0 to Sub DSP Ground +2.5V power supply (for internal core logic) Output of bitstream or PCM data from DIR DIR: Serial data word clock (fs) output DIR: Serial data bit clock (64fs) output DIR: Serial data master clock (256fs or 128fs) output DIR: Data error detect / Block start output DIR: Serial data synchronized timing / User data output DIR: Serial data master clock 128fs / Channel status output DIR: Double rate lock detect / Validity flag output Word clock input for SDIB, SDOB Bit clock input for SDIB, SDOB Ground PCM data output from Sub DSP PCM data output from Sub DSP PCM data output from Sub DSP PCM data output from Sub DSP +3.3v power supply (for I/O)
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YSS932
No. Name I/O O O O O O O O O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O O O O O O O O O O O O O O O O O O O O O O O O Function General purpose output port General purpose output port General purpose output port General purpose output port General purpose output port General purpose output port General purpose output port General purpose output port Ground +2.5V power supply (for internal core logic) Sub DSP: External memory interface Data 0 Sub DSP: External memory interface Data 1 Sub DSP: External memory interface Data 2 Sub DSP: External memory interface Data 3 Sub DSP: External memory interface Data 4 Sub DSP: External memory interface Data 5 Sub DSP: External memory interface Data 6 Sub DSP: External memory interface Data 7 Ground +3.3V power supply (for I/O) Sub DSP: External memory interface Data 8 Sub DSP: External memory interface Data 9 Sub DSP: External memory interface Data 10 Sub DSP: External memory interface Data 11 Sub DSP: External memory interface Data 12 Sub DSP: External memory interface Data 13 Sub DSP: External memory interface Data 14 Sub DSP: External memory interface Data 15 Sub DSP: External DRAM interface Column address strobe output Sub DSP: External memory interface Write enable output Sub DSP: External memory interface Output enable output Sub DSP: External DRAM interface Row address strobe output Ground +3.3V power supply (for I/O) Sub DSP: External memory interface Address 8 Sub DSP: External memory interface Address 7 Sub DSP: External memory interface Address 0 Sub DSP: External memory interface Address 6 Sub DSP: External memory interface Address 1 Sub DSP: External memory interface Address 5 Sub DSP: External memory interface Address 2 Sub DSP: External memory interface Address 4 Sub DSP: External memory interface Address 3 Sub DSP: External memory interface Address 9 Sub DSP: External memory interface Address 10 Sub DSP: External memory interface Address 11 Ground +2.5V power supply (for internal core logic) Sub DSP: External memory interface Address 12 Sub DSP: External memory interface Address 13 Sub DSP: External memory interface Address 14 Sub DSP: External memory interface Address 15 Sub DSP: External memory interface Address 16 Sub DSP: External memory interface Address 17 Sub DSP: Overflow / Program end detect 56 OPORT0 57 OPORT1 58 OPORT2 59 OPORT3 60 OPORT4 61 OPORT5 62 OPORT6 63 OPORT7 64 VSS 65 VDD2 66 RAMD0 67 RAMD1 68 RAMD2 69 RAMD3 70 RAMD4 71 RAMD5 72 RAMD6 73 RAMD7 74 VSS 75 VDD1 76 RAMD8 77 RAMD9 78 RAMD10 79 RAMD11 80 RAMD12 81 RAMD13 82 RAMD14 83 RAMD15 84 CASN 85 RAMWEN 86 RAMOEN 87 RASN 88 VSS 89 VDD1 90 RAMA8 91 RAMA7 92 RAMA0 93 RAMA6 94 RAMA1 95 RAMA5 96 RAMA2 97 RAMA4 98 RAMA3 99 RAMA9 100 RAMA10 101 RAMA11 102 VSS 103 VDD2 104 RAMA12 105 RAMA13 106 RAMA14 107 RAMA15 108 RAMA16 109 RAMA17 110 OVFB/END
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YSS932
No. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Name ZEROFLG VSS NONPCM DTSDATA AC3DATA MUTE KARAOKE VDD1 SURENC CRC /LOCK DIRINT /CS SO SI SCK /IC VSS I/O O O O O O O O O O O Is Ot Is Is Is Function Main DSP: Zero flag output Ground Main DSP: non-PCM data detect Main DSP: DTS data detect Main DSP: AC-3 data detect Main DSP: Auto mute detect Main DSP: AC-3 Karaoke data detect +3.3V power supply (for I/O) Main DSP: AC-3 2/0 mode Dolby Surround Encode input detect Main DSP: AC-3 CRC error detect DIR: PLL lock detect DIR: interrupt output Microprocessor interface Chip select input Microprocessor interface Data output Microprocessor interface Data input Microprocessor interface Clock input Initial clear input Ground
I : Input pin Is : Schmitt trigger input pin I+ : Input pin with a pull-up resistor O : Output pin Ot : Tri-state output pin A : Analog pin
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YSS932
FUNCTION DESCRIPTION
YSS932 consists of three blocks; the Main DSP block where AC-3 / Pro Logic II / DTS decoding is executed, the Sub DSP block where various sound field effects are added and the SPDIF receiver (DIR) block. The Sub DSP is a 8 channel input / 8 channel output programmable DSP exclusively for sound field processing. It can apply such effects as simulation surround, output configuration and virtual surround. In addition, with SRAM or DRAM connected, it can produce reverberation up to 2.73 seconds delay at fs=48kHz. By using this function, it is possible to simulate various sound fields such as a hall or a church. The SPDIF receiver (DIR) can handle the digital audio interface format input signals of the sampling frequency 32kHz through 96kHz.
Note) If adopting some technology owned by another company is desired for use in Sub DSP block, note that a separate contract may be required between the owner of that technology and the user with respect to adoption of the technology.
PIN DESCRIPTION 1) DIR Block
1-1) Digital audio interface signal input DDIN0-3 Input digital audio interface format signal (DAIF signal) into these pins. Then the signal selected by control register DDINSEL0, 1 is input to the DIR block. As the pull-up resistors are not built in, connect the unnecessary pins to VSS.
Also, DDIN1, 2, 3 are served as IPORT5, 6, 7. If they are not used as DDIN input pins, they are usable as general purpose input ports.
1-2) Clock DIRMCK The master clock for such peripheral devices as DAC and ADC is output. The operation mode of DIRMCK is selected according to the lock condition of PLL in the DIR block and settings for the control register. The DIRMCK output modes are as follows.
- When PLL in the DIR block is not locked (/LOCK=H) ----- (1) DIRMCK outputs 12.288MHz. - When PLL in the DIR block is locked (/LOCK=L) and CKMOD=1 ----- (2) DIRMCK outputs 12.288MHz - When PLL in the DIR block is locked (/LOCK=L) and CKMOD=0 DIRMCK outputs according to the setting of LOCKMOD1-0.
LOCKMOD1 0 0 1 LOCKMOD0 0 1 Normal rate 256fs 256fs 256fs Double rate 256fs 128fs 12.288MHz -(3)
The mode like the above (1), (2) and (3) in which the XI's divided clock of 12.288 MHz is output from DIRMCK is referred to as "free-run mode".
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YSS932
DIRBCK, DIRWCK, FS128, SYNC The clock for such peripheral devices as DAC and ADC is output. At CMOD=0 setting, FS128 is output from FS128/C pin and at UMOD=0 setting, SYNC is output from SYNC/U pin. DIRBCK, DIRWCK and FS128 are obtained by dividing the clock of DIRMCK and the period of each clock is as follows.
DIRBCK DIRWCK FS128 64fs fs 128fs
SYNC is output according to the following timing. Note) At settings of DIROWP=0, DIROBP=0
Rch Lch Lch Rch
DIRWCK DIRBCK FS128 SYNC
1-3) Serial data output DIRSDO The DAIF signal data is output. The output is always 24-bit width including audio auxiliary bit. The data is output from the DIRSDO pin as well as goes into the Main DSP block through the SDIA interface.
It must be noted that the data output from the DIRSDO pin is muted during the free-run mode or at SDOMUTE=1 setting, but the data output to the Main DSP is muted only during the free-run mode regardless of SDOMUTE setting. The output format can be selected by setting the DIR SDO register. For the details of the format, refer to "Serial Data Interface Format".
1-4) Status data output BS, V, U, C The data of block start, validity flag, user data and channel status obtained from the DAIF signals are output as described below.
The block start is output from the ERR/BS pin at BSMOD=1 setting. The validity flag is output from the DBL/V pin at VMOD=1 setting. The user data is output from the SYNC/U pin at UMOD=1 setting. The channel status is output from the FS128/C pin at CMOD=1 setting. BS, V, U, C are fixed to the "L" level during the free-run mode or at VUCMUTE=1 setting.
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YSS932
BS, V, U and C are output according to the format shown below. Alphabet clusters in the figure represent: VLn --- Validity flag of L-ch frame n VRn --- Validity flag of R-ch frame n ULn --- User data of L-ch frame n URn --- User data of R-ch frame n CLn --- Channel status of L-ch frame n CRn --- Channel status of R-ch frame n When in mode 0 (CTIMMOD=0) Note) at settings of DIROWP=0, DIROBP=0
DIRWCK BS V U C
VL190 VR190 VL191 VR191 VL0 VR0 VL1 VR1
UL190
UR190
UL191
UR191
UL0
UR0
UL1
UR1
CL190
CR190
CL191
CR191
CL0
CR0
CL1
CR1
DIRWCK DIRBCK BS, V, U, C
When in mode 1 (CTIMMOD=1) Note) at settings of DIROWP=0, DIROBP=0
DIRWCK BS V U C
VL190 VR190 VL191 VR191 VL0 VR0 VR31 VL32 VR32
UL190
UR190
UL191
UR191
UL0
UR0
UR31
UL32
UR32
CL190
CR190
CL191
CR191
CL0
CR0
CR31
CL32
CR32
DIRWCK DIRBCK BS, U, C V
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YSS932
/LOCK, ERR, DIRINT The same data as LOCKN, DIRERR, DIRINT of DIR STATUS Register are output from /LOCK, ERR/BS, DIRINT pins respectively. The DIRERR data is output from ERR/BS pin at BSMOD=0 setting. DBL The information, whether the DDIN input signal is a double rate signal, is output from the DBL/V pin at VMOD=0 setting. If PLL in the DIR block is locked at double rate and the free-run mode is not used, "H" level is output. If PLL in the DIR block is locked at normal rate or the free-run mode is used, "L" level is output.
1-5) Analog circuit for PLL in DIR block DIRPCO, DIRPRO These are capacitor and resistor connection pins for PLL in DIR block. As shown below, connect a 4700pF capacitor and an 8.2k resistor between DIRPCO and AVSS as close as physically possible to DIRPCO and a 5.1k resistor between DIRPRO and AVSS as close as physically possible to DIRPRO.
DIRPCO
DIRPRO
5.1k
8.2k 4700pF
AVSS
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YSS932
2) Main DSP Block
2-1) Serial data input / output SDIA This is used to input PCM or bitstream into the Main DSP block. Normally, the PCM output of the external ADC is input. The input format can be selected by setting the SDIA register. For the format, refer to "Serial Data Interface Format". The SDIA pin input or DIRSDO output of the DIR block is selected by SDIASEL, and processed in the Main DSP block. SDOA0-2 The PCM signal processed in the Main DSP block is output to these pins. L-ch, R-ch signals are output from SDOA0 pin, LS-ch, RS-ch signals from SDOA1 pin and C-ch, LFE-ch signals from SDOA2 pin. At the same time the signals are output from these pins, they are input to the Sub DSP block through the SDIB interface. The output format can be selected by setting the SDOA register. For the format, refer to "Serial Data Interface Format". SDBCKI0, SDWCKI0, SDBCKI1, SDWCKI1 These are input clocks for the serial data. When the serial data is synchronized not to DIRBCK, DIRWCK from DIR included in this LSI but to the clocks from the outside, supply clocks to these pins. The clocks for the SDIA / SDOA interface will be DIRBCK / DIRWCK or SDBCKI0 / SDWCKI0 selected at SDIACKSEL. The clocks for the SDIB / SDOB interfaces will be the same clocks for the SDIA interface (DIRBCK / DIRWCK or SDBCKI0 / SDWCKI0 selected at SDIACKSEL) or SDBCKI1 / SDWCKI1 (Refer to "Block Diagram".) When not using the external clock, keep these pins unconnected. /SDBCKO A reverse clock of DIRBCK or SDBCKI0 selected at SDIACKSEL is output. This clock can be utilized when the polarity of the clock for the peripheral devices such as ADC and DAC differs. Refer to "Block Diagram".
2-2) Status output DTSDATA, AC3DATA, SURENC, KARAOKE, MUTE, CRC, NONPCM These pins output the status data of the signals processed in the Main DSP block. The status, which is the same as the contents of the STATUS Register, is output from respective pins. ZEROFLG This pin indicates how long the input signal (SDIA or DIRSDO) for the Main DSP block is kept in the digital zero state. The same status as ZEROFLG of the ZERO Register is output.
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YSS932
3) Sub DSP Block
3-1) Serial data input / output SDIB0-3 These are PCM input pins to the Sub DSP block. The data input to SDIB0-2 pins or the SDOA0-2 output from the Main DSP block are selected at SDIBSEL and processed in the Sub DSP block. The input data to the SDIB3 pin is always processed in the Sub DSP block regardless of SDIBSEL. Refer to "Block Diagram".
The input format can be selected by setting the SDIB register. For the format, refer to "Serial Data Interface Format".
SDOB0-3 These are the output pins for the PCM signals processed in the Sub DSP block. The output format can be selected by setting the SDOB register. For the format, refer to "Serial Data Interface Format".
3-2) External memory interface RAMA0-17, RAMD0-15, RAMWEN, RAMOEN, CASN, RASN These pins are used to connect an external memory to the Sub DSP block for the data delay.
3-3) Status output OVFB/END The output varies depending on OVFSEL settings of ERAM register bit 7. This output is used when programming Sub DSP.
OVFB at OVFSEL=0 This pin becomes "H" level when a digital overflow occurs as a result of operation in the Sub DSP block. "H" level is kept from the moment an overflow occurs to the moment the next PCM sample is output from the SDOB interface. When the next PCM sample output starts, the pin is reset to "L" level. END at OVFSEL=1 This pin becomes "H" level while the program counter of Sub DSP is operating, and "L" level when all the processing is completed and the program counter stops. While operating correctly, it becomes "L" level once during one sample time. If it fails to become "L" level even once during one sample time, it means that the program has not been completed correctly and fully.
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YSS932
4) Microprocessor Interface
/CS, SCK, SI, SO The control registers are read / written via the four-wire serial microprocessor interface. For the interface format, refer to "Microprocessor Interface Format". IPORT0-4, DDIN1-3 The signals input to these pins can be read via the IPORT register. By connecting the status output of other devices to these pins, it is possible to read the data of other devices via the microprocessor interface of this device. It should be noted that DDIN1-3 are also used as input signal pins of DIR block. IPORT0-4 pins may be left open when unused as pull-up resistors are built-in, but be sure to connect the unused DDIN1-3 pins to VSS as no pull-up resistors are built-in. OPORT0-7 The data written in the OPORT register are output from these pins. By connecting the mode selection of other devices to these pins, the other device can be controlled via the microprocessor interface of this device.
5) Clock
XI, XO These are crystal oscillator (24.576MHz) connection pins. Use a crystal oscillator of fundamental mode. Use XI when inputting the external clock. CPO This is to connect external parts for PLL generating the operation clock of the DSP block. Connect a resistor and capacitors between CPO and AVSS as close as physically possible to CPO.
CPO
1k 470pF 4700pF
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YSS932
Control Register / Register Map
The decoding system is controlled by reading and writing the control registers as shown below through microprocessor interfaces (/CS, SCK, SI, SO). All control registers are reset to "0" by initial clear (/IC=L).
Address
Name 0x00 AUTO/DSN 0x01 MUTE 0x02 SDIA 0x03 SDOA 0x04 OPORT 0x05 IPORT 0x06 (TEST) 0x07 (TEST) 0x08 PCM 0x09 NOISE LEVEL 0x0A CENTER DELAY 0x0B SURROUND DELAY 0x0C NOISE 0x0D FS 0x0E L VOLUME 0x0F C VOLUME 0x10 R VOLUME 0x11 LS VOLUME 0x12 RS VOLUME 0x13 LFE VOLUME 0x14 COMPRESSION 0x15 HDYNRNG 0x16 LDYNRNG 0x17 MODE 0x18 | 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 BITSTREAM
bit 7 bit 6 AUTOMOD LMUTEN CMUTEN SDIACKSEL SDIASEL
bit 3 bit 2 bit 1 bit 0 DSNIGN DSN2-0 RMUTEN RSMUTEN LSMUTEN LFEMUTEN DSPMUTEN AMOFF SDIAFMT1-0 SDIABIT1-0 SDIAWP SDIABP SDOAFMT1-0 SDOABIT1-0 SDOAWP SDOABP OPORT7-0 IPORT7-0
bit 5
bit 4
PLDECMOD1-0
PCMDLY
LROUT NOISELEV7-0 CDELAY2-0 SRDELAY3-0
NOISE
PN/WN IMPULSE CWCFG2-0
EMPON
AIBON
VOLON
PCMMOD PLDECON
RSINV
DIMCFG2-0 SRFIL1-0 FS2-0 LVOL7-0 CVOL7-0 RVOL7-0 LSVOL7-0 RSVOL7-0 LFEVOL7-0 DITHOFF P11OFF DIALOFF COMPMOD1-0 HDYNRNG7-0 LDYNRNG7-0 DUALMOD1-0 OUTMOD2-0
(described in the later section)
(Unused) (Undefined) (Unused) (Undefined) Pc Pc7-0 DATA STREAM STREAM7 STREAM6 STREAM5 STREAM4 STREAM3 STREAM2 STREAM1 STREAM0 STATUS DTSDATA AC3DATA 2/0MODE SURENC KARAOKE MUTE CRC NONPCM ZERO ZEROFLG ZERO6-0 (TEST) MPCNT_H MPLOAD MPCLEARN MPCNT11-8 MPCNT_L MPCNT7-0 SDIB SDIBFMT1-0 SDIBBIT1-0 SDIBWP SDIBBP SDIBCKSEL SDIBSEL SDOB SDOBFMT1-0 SDOBBIT1-0 SDOBWP SDOBBP SDOBCKSEL ERAM OVFSEL JMPSEL RASREF ERAMMOD ERAMSEL1-0 (TEST)
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YSS932
0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 | 0x57 0x58 | 0x7F MI0 MI1 MI2 MI3 MI4 MI5 MI6 MI7 DIR CTRL DIR SDO DIR PIN DIR INTMOD (TEST) DIR CUADR DIR CUDAT DIR STATUS DIR FS (TEST) MI0REG7-0 MI1REG7-0 MI2REG7-0 MI3REG7-0 MI4REG7-0 MI5REG7-0 MI6REG7-0 MI7REG7-0 CKMOD VUCMUTE SDOMUTE LOCKMOD1-0 DIROFMT1-0 DIROBIT1-0 BSMOD VMOD UMOD CMOD INTMOD6-1 DHLD DIRINT R/L DIRERR U/C LOCKN CUDAT7-0 VFLAG CSB1 CSB3 CUADR4-0 CSCHG BSFLAG (Undefined) DIRFS2-0 DDINSEL1-0 DIROWP DIROBP CTIMMOD
Invalid
The output at the SO pin becomes High-Z.
Never write "1" into the shaded bits because the bits for testing are assigned there. Never make an access to addresses 0x06, 0x07, 0x31, 0x37, 0x44, 0x49 to 0x57 because the registers for testing are assigned there.
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YSS932
The contents of the bitstream register (addresses 0x18 to 0x2A) vary depending on the input signal, i.e., the Main DSP input signal is AC-3 bitstream, DTS bitstream or PCM as shown below. Only reading is allowed with the BITSTREAM register and not writing.
1) When the input signal is AC-3 bitstream
Address
Name bit 7 bit 6 BITSTREAM 0 fscod BITSTREAM 1 BITSTREAM 2 acmod BITSTREAM 3 dsurmod BITSTREAM 4 0 0 BITSTREAM 5 0 0 BITSTREAM 6 audprodie BITSTREAM 7 audprodi2e BITSTREAM 8 timecod1e 0 (when bsid=6) (xbsi1e) (0) 0x21 BITSTREAM 9 (when bsid=6) (ltrtsurmixlev) 0x22 BITSTREAM 10 timecod2e 0 (when bsid=6) (xbsi2e) (0) 0x23 BITSTREAM 11 (when bsid=6) 0x24 BITSTREAM 12 langcode langcod2e 0x25 BITSTREAM 13 0x26 BITSTREAM 14 0x27 BITSTREAM 15 0x28 BITSTREAM 16 0x29 BITSTREAM 17 0x2A BITSTREAM 18 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20
bit 5 bsid copyrightb 0 0
bit 4
bit 3 bit 2 frmsizecod
bit 1
bit 0
cmixlev origbs 0
mixlevel mixlevel2 (dmixmod) timecod1 (lorocmixlev) (dsurexmod)
bsmod surmixlev lfeon 0 0 0 dialnorm dialnorm2 roomtyp roomtyp2 timecod1 (ltrtcmixlev) (ltrtsurmixlev) (lorosurmixlev)
timecod2 (dheadphonmod)
(adconvtyp)
(xbsi2) (encinfo) 0
compre
timecod2 (xbsi2) compr2e 0 langcod langcod2 compr compr2 dynrng dynrng2
0
0
2) When the input signal is DTS bitstream
Address
0x18 0x19 0x1A 0x1B 0x1C | 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A
Name BITSTREAM 0 BITSTREAM 1 BITSTREAM 2 BITSTREAM 3 BITSTREAM 4 | BITSTREAM 11 BITSTREAM 12 BITSTREAM 13 BITSTREAM 14 BITSTREAM 15 BITSTREAM 16 BITSTREAM 17 BITSTREAM 18
bit 7
bit 6 bit 5 bit 4 fscod (Undefined) (Undefined) HDCD AMODE (Undefined)
bit 3
bit 2 bit 1 bit 0 RATE EXT_AUDIO_ID EXT_AUDIO (Undefined) lfeon PCMR
(Undefined) (Undefined) DYNF (Undefined) (Undefined) RANGE (Undefined) (Undefined) (Undefined) (Undefined)
3) When the input signal is PCM
The contents of BITSTREAM register (addresses 0x18 to 0x2A) are all undefined.
17
YSS932
Serial Data Interface Format
Shown below are interface formats obtained by setting SDIA Register, SDOA Register, SDIB Register, SDOB Register and DIR SDO Register.
1 Frame Lch (Ls,Cch)
WP=0
Rch (RS,LFEch)
WCK
WP=1
BP=0
BCK
BP=1
FMT1-0=00 BIT1-0=XX
No Delay
M L M L
FMT1-0=10 BIT1-0=XX
1 bit Delay
M L M L
DATA
FMT1-0=01 BIT1-0=00 FMT1-0=01 BIT1-0=01 FMT1-0=01 BIT1-0=10 FMT1-0=01 BIT1-0=11 L L L
EIAJ
L M 87 L M 87
M
65
L
M
65
M
43
L
M
43
M
L
M
L
M : MSB
L : LSB
18
YSS932
Microprocessor Interface Format
A four-wire serial interface is used to read and write the control registers.
/CS SCK
write R/W = L
SI SO
Don't Care
A0
A1
A2
A3
A4
A5
A6 R/W D0
D1
D2
D3
D4
D5
D6
D7
Don't Care
High-Z
read R/W = H
SI SO
Don't Care
A0
A1
A2
A3
A4
A5
A6 R/W
Don't Care
Don't Care
High-Z
D0
D1
D2
D3
D4
D5
D6
D7
High-Z
SO becomes an output pin only when all of the following conditions are met. - /CS=L - When reading the valid addresses - Timing of 8 bits data output If any of the above conditions is not met, SO outputs High-Z. Thus SO, SI and SCK can be used jointly with other devices that have similar interfaces. [CAUTION] Set /CS=H during /IC=L.
19
YSS932
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power Supply Voltage Symbol VDD1 AVDD VDD2 VI Tstg Condition Min. Vss-0.5 Vss-0.5 Vss-0.5 -0.5 -0.5 -50 Typ. Max. 4.6 4.6 3.6 5.75 VDD1+0.5 125 Unit V V V V V C
Input Voltage Storage Temperature
except XI pin *1 XI pin
*1: 5V tolerant input terminal is used.
2. Recommended Operating Conditions
Parameter Power Supply Voltage Symbol VDD1 AVDD VDD2 Top Condition Min. 3.0 3.0 2.3 0 Typ. 3.3 3.3 2.5 25 Max. 3.6 3.6 2.7 70 Unit V V V C
Operating Temperature
2. DC Characteristics
Conditions: Under recommended operating conditions
Parameter Input Voltage "H" level 1 Input Voltage "L" level 1 Input Voltage "H" level 2 Input Voltage "L" level 2 Input Voltage "H" level 3 Input Voltage "L" level 3 Output Voltage "H" level Output Voltage "L" level Input Leakage Current Pull-up Resistor Power Consumption Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH VOL ILI RU PD1 PD2 Condition *1 *1 *2 *2 *3 *3 IOH = -80 A IOL = 1.0 mA no pull-up resistor pin VDD1 VDD2 Min. 0.7VDD1 2.4 0.8 2.2 0.8 VDD1-0.4 -10 40 60 220 0.4 10 160 120 260 Typ. Max. 0.3VDD1 Unit V V V V V V V V A k mW mW
*1: Applicable to XI pin. *2: Applicable to /IC and DDIN0-3 pins. *3: Applicable to input pins except the above pins.
20
YSS932
SYSTEM CONNECTION DIAGRAM
Shown below is an example of basic connection of YSS932 (AC3D3B) and the peripheral circuits.
/IC
HOST PROCESSOR
(fs) (64fs) (256fs)
10k 0.1uF
DIRWCK
DIRMCK
DIRBCK
SCK
SI
/IC TESTR1
/CS
SO
SDOB0
DAC
L R
DAIF (SPDIF)
(256fs) (64fs) (fs)
DDIN0 DDIN1 DDIN2 DDIN3
8.2k
SDOB1
DAC
LS RS
4700pF 5.1k
DIRPCO DIRPRO AVSS
YSS932 (AC3D3B)
SDOB2
RAMD0-15 CASN RASN RAMWEN RAMOEN RAMA0-17
DAC
C LFE
L R
CPO
TESTXI
ANALOG
ADC
SDIA
XO
SDOB3
24.576MHz
470pF
XI
DAC (option)
1k 4700pF
SRAM or DRAM (option)
21
YSS932
EXTERNAL DIMENSIONS
22
YSS932
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL, OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANY THIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRANGIMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.
Notice
The specifications of this product are subject to improvement changes without prior notice.
AGENCY
Address inquiries to: Semiconductor Sales & Marketing Department Head Office Tokyo Office Osaka Office 203, Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192, Japan Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568, Japan Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 3-12-12, Minami Senba, Chuo-ku, Osaka City, Osaka, 542-0081, Japan Tel. +81-6-6252-6221 Fax. +81-6-6252-6229
All rights reserved
2003
Printed in Japan

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